1. Technical Field
The disclosure in generally relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a memory device.
2. Description of the Related Art
Non-volatile memory (NVM) which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell has been widely adopted by bulk solid state memory applications in portable audiovisual entertainment devices, cell phones or digital cameras etc. Recently, various three dimensional (3D) memory devices, such as a 3D single gate vertical-channel (SGVC) flash memory device that has a multi-layer stack structure may possess a higher density memory and excellent electrical characteristics, e.g. reliability in data storage and high operating speed, has been provided in order to accommodate the rising demand for superior memory.
However, as semiconductor features shrink in size and pitch, the problems of degradation in electrical properties and device operation due to inter-cell interference between adjacent memory cells is getting worse. In order to solve the problems, air gaps disposed between gates of two adjacent memory cells are applied to reduce cell-to-cell interference.
A typical method for fabricating a 3D SGVC flash memory device with air gaps comprises steps as follows: A plurality of word line trenches are formed in a multi-layer stack, and a memory layer and a channel layer are formed in sequence on the bottoms and sidewalls of the word line trenches, such that a plurality of gaps are formed between the channel layer conformal to the vertical sidewalls of the word line trenches. Next, a plurality of bit line openings are formed to remove portions of the memory layer and the channel layer that are disposed in the word line trenches, so as to define a plurality memory cells connected in series and disposed on the vertical sidewalls of the word line trenches. Since the etching gas used to form the bit line openings may flow along the gaps, thus the word line trenches may be permeated with the etching gas and the portions of memory layer and the channel layer that are disposed in the word line trenches used to form the memory cells may be damaged. As a result, the pattern of the bit line openings may be misaligned and device failure of the 3D SGVC flash memory may occur.
Therefore, there is a need of providing an improved method for fabricating a memory device to obviate the drawbacks encountered from the prior art.